library ieee;
use ieee.std_logic_1164.all;

entity full_adder is
   port (cin, a, b : in std_logic;
         f, cout : out std_logic);
end full_adder;

architecture structure of full_adder is
   begin
      f <= (a xor b) xor cin;
      cout <= (a and b) or ( (a xor b) and cin);
end structure;
